This invention relates to a semiconductor device and fabrication thereof and, more particularly, to transistor formation in a semiconductor device and fabrication thereof.
Semiconductor devices, including logic devices, embedded memory devices and memory devices, utilize Field Effect Transistors (FETs), which may use both N+ and P+ doped polysilicon gates. However, using both types of transistor gates in the same device creates challenges in the fabrication process. Many memory devices utilize both N+ and P+ polysilicon gates and thus exhibit fabrication issues that require attention to obtain quality devices at the lowest production price possible.
For example, during Static Random Access Memory (SRAM) fabrication, when both N+ and P+ polycrystalline silicon (or germanium) are used as the transistor gate electrodes (known in the art as wordline gate electrodes), it is difficult to form good wordline etch profiles for both N-channel and P-channel transistors without pitting the silicon substrate, due to the different etching characteristics of a P-type doped polysilicon versus an N-type doped polysilicon.
The difficulty increases when thinner gate oxide is used fabricate smaller geometric devices. Furthermore, if a Self Aligned Contact (SAC) etch is desired to open access to the source/drain areas of the transistor, it requires a tall wordline stack with an oxide/nitride cap deposited on top of the wordline gate electrodes. The taller wordline stack used for a process flow with SAC etch makes it more difficult to etch than process flows that use a salicide process due to the higher aspect ratio during the etch process. For example, the SAC etch has to etch through the entire gate stack comprising an oxide (or nitride) cap, a WSix (or W) layer and a polysilicon layer. On the other hand a silicide process needs to only etch through a polysilicon layer.
The present invention comprises a method to form transistors with highly desirable transistor gate profiles.
A significant focus of an exemplary implementation of the present invention includes a method of forming transistors, such as p-channel and n-channel devices, during v semiconductor fabrication.
An exemplary implementation of the present invention comprises a semiconductor fabrication method of forming a pair of transistor gates of opposite conductivity type by partially forming first and second gate stacks comprising an insulation layer, a conductive layer and polysilicon layer for the pair of transistor by removing a portion of the polysilicon layer. The polysilicon layer includes a dominant region of first-type conductive dopants and a dominant region of second-type conductive dopants. A first-type conductive transistor gate is formed by, completing the formation of the first gate stack and a second-type conductive transistor gate is formed by completing the formation of the second gate stack separately from the formation of the first-type transistor gate.